U.S. Pat. No. 6,510,191 “Direct Digital Synthesizer Based on Delay Line with Sorted Taps,” to Bockelman, and assigned to Motorola, the assignee of the present application, relates to a method of providing a time resolution increase in a clock generation circuit by use of a delay line having a number of delay taps. In this circuit, the series connected delay line elements form a part of the path of the output signal being synthesized. As a result, all of the delay line imperfections such as accumulated mismatch, delay lock loop offset error, and summed thermal noise can impact the output signal quality. Some or all of this error can be removed using calibration techniques in certain circumstances.